This invention relates to a non-volatile memory cell and a manufacturing process therefor, in particular a process employing suicides.
The invention relates to a non-volatile memory cell integrated in a semiconductor substrate and comprising:
a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate and between said first source and drain regions; and
a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate, between said second source and drain regions.
Specifically, the invention relates to a process for manufacturing such a cell.
The invention relates in particular, but not exclusively, to the manufacturing process of a non-volatile memory cell, e.g. EEPROMs of the FLOTOX type, and the description that follows will cover this field of application for convenience of explanation.
As is well known, the current technology for manufacturing semiconductor integrated circuits has succeeded in greatly reducing the resistance of interconnects and contact pads in the active areas of the individual devices, through the use of composite materials of silicon and a transition metal such as titanium or tungsten. These composite materials are known as silicides, and used for forming layers with relatively low resistivity.
These silicide layers cannot be used to fabricate devices having non-volatile memory cells, such as EEPROMs, Flash-EEPROMs or EPROMs, integrated therein, because relatively high voltages must be used for programming such memory cells, and the managing of these voltages is incompatible with silicidation processes.
In fact, these memory devices must be provided with lightly doped drain and source regions in order to stand such voltages.
The process employed to produce silicide layers may, however, cause problems in these relatively thin and lightly doped regions. During the thermal process for reacting the transition metal layer with the substrate surface and forming the silicide layer, a surface layer of the substrate is expended, and some dopant from the substrate is taken up by the silicide layer so that, during normal operation, the silicide layer becomes shorted to the substrate.
In addition, high strength electric fields develop between the active area and the isolation region, at the cell drain region contact.
Sometimes, the contact size is larger than that of the active area, and results in a short circuit forming between the silicized junction and the substrate of different concentration.
Even where the contact is fully contained within the active area, the voltage applied to it would be transferred into the silicized region up to the border region of the isolation region.
An embodiment of this invention provides a non-volatile memory cell with good performance in terms of access time, and overcomes the limitations of prior art structures.
An object of the inventive process is to arrange for the lightly doped regions of the memory cells to be screened without requiring additional process steps.
The embodiment provides a memory cell with silicide layers to improve the cell access time.
The features and advantages of the memory cell according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.